During 50 years, semiconductor technology has been evolving in exponential rates in both productivity and performance. By following a steady technological path that consists in scaling down transistors and increasing electronic components density, the semiconductor industry was able to meet the increasing demand in high performance, low power consumption and low cost devices. However by constantly shrinking devices geometries and increasing functionalities, semiconductor industry is facing physical limitations in addition to more and more overwhelming parasitic effects. Since further miniaturisation would be made impossible in a near future, 3D integration appears as a promising approach to go beyond planar integration possibilities. This approach allows high performances and various functionalities compounds achievements. 3D integration consists on various chips stacking with vertical and electrical interconnects. The metallic direct bonding offers strong mechanical bond with a good electrical conductivity between the two bonded circuits. In this work, electrical behaviours of bonded devices achieved by direct bonding are studied. First, the various structures layout used in this study and the process flow integration for the 3D demonstrator are described. Then, electrical characterization of metallic interconnects are performed. Measurements and results are reported and discussed concerning the study of resistance evolution of the bonding interface during anneal. And the investigation of the bonded devices behaviours facing the risk of reliability issues on Cu-Cu direct bonded interconnects are achieved by addressing electromigration items and several thermal stress tests as stress voiding or thermal cycling. Finally, physical characterizations enabled failure mechanisms analysis and identification. technological steps required for a chip to wafer integration using direct bonding process has been developed and studied during this work. Results are given at the end of this report.
