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Resistive-Open Defect Analysis for Through-Silicon-Vias
International audience -
New concepts for the 3D integration and cooling of vertical power semiconduct...
The power electronics field is struggling for new material, technological and conceptual evolutions. These changes induce breakthrough in the conventional design and... -
Development of copper electroplating processes for Through Silicon Via (TSV) ...
Nowadays, 2D integration shows serious limitations when it comes to manufacturing devices with increased functionality and performance. In this context, 3D integration... -
Analysis and optimization of electrical performance of interconnections netwo...
This PhD work deals with characterization and electrical modeling of interconnection networks for 3D stacking of advanced integrated circuits. First, characterization... -
Array of tunable Fabry Perot filters in 3D MOEMS integration technology : App...
Multispectral imaging is used to improve target detection and identification in monitoring applications. It consists in analyzing images of the same scene... -
Performance analysis and optimization of high density tree-based 3d multileve...
International audience -
High Performance 3-Dimensional Heterogeneous Tree-based FPGA Architectures (H...
International audience -
Development of HW/SW Fault Tolerant and Self-Configuring Architectures for 3D...
3D technology promises energy-efficient heterogeneous integrated systems, which may open the way to thousands cores chips. Silicon dies containing processing elements... -
Architecture level optimization of 3-dimensional tree-based FPGA
International audience -
Investigation of the mechanisms involved in room temperature metal and oxides...
Direct wafer bonding refers to a process by which two mirror-polished wafers are put into contact and held together at room temperature without any additional... -
Selection of a precursor for the atomic layer deposition of copper : applicat...
With the increasing density of features in the various integrated circuits surrounding us, 3D integration (stacking chips) becomes essential. One key point of such... -
3D Integration of Si/SiGe heterostructured nanowires for nanowire transistors.
The goal of this thesis is to build and characterize nanowire based field-effect-transistors. These FET will have either back or wrapping gate using standard CMOS... -
Mechanical characterization and modeling of thin films for processing of micr...
The fabrication of microelectronic devices using 3D integration technologies requires a good knowledge of mechanical issues. Indeed, the thin films that are integrated...
