Architecture level optimization of 3-dimensional tree-based FPGA
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | ISSN: 0026-2692 |
| Author | Pangracious, Vinod, Amouri, Emna, Marrakchi, Zied, Mehrez, Habib |
| Maintainer | CCSD |
| Last Updated | May 6, 2026, 21:32 (UTC) |
| Created | May 6, 2026, 21:32 (UTC) |
| Identifier | hal-00944759 |
| Language | en |
| Rights | https://about.hal.science/hal-authorisation-v1/ |
| contributor | Circuits Intégrés Numériques et Analogiques (CIAN) ; Laboratoire d'Informatique de Paris 6 (LIP6) ; Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS) |
| creator | Pangracious, Vinod |
| date | 2014-04-06T00:00:00 |
| harvest_object_id | 7c49947c-b622-440b-ab09-6f4e399d5f59 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2023-04-11T00:00:00 |
| relation | info:eu-repo/semantics/altIdentifier/doi/10.1016/j.mejo.2013.12.011 |
| set_spec | type:ART |