Achieved at the beginning of the integrated circuits manufacturing, shallow trench isolation permits to electrically isolate transistors from each other's to avoid current leakage. Trenches are filled with silicon dioxide film deposited by chemical vapor deposition (also called CVD). Trenches gap-filling is usually performed by TEOS/O3 Sub-Atmospheric Chemical Vapor Deposition (TEOS/O3 SACVD). However, trenches gap-filling with SACVD process reveals some limitations for advanced technology nodes (mainly 28 nm & 14 nm) due to quasi-vertical trenches profile and slope sensitivity of SACVD, which can lead to voids formation in gap-filling oxide and consequently to electrical isolation failure. To solve this issue, a new three steps gap-fill strategy is proposed for the CMOS 14 nm technology node. During the first step, a thin oxide liner is deposited into trenches. Then, in the second step, film sidewalls are etched with an innovative process, based on downstream plasma of NF3/NH3, to create tapered profile favorable for final SACVD gap-fill achieved in the third step. The development of this strategy has followed three work leads. First, the deposition process has been characterized to select best conditions for the first step. Then, the innovative etching process has been widely characterized. The influence of etching parameters has been studied on blanket and patterned wafers to understand etching mechanisms and slope modification. Finally, the gap-fill strategy has been developed and integrated for the CMOS 14 nm technology node. We demonstrate that it is possible to control the slope modification by tuning etching conditions and that strategy allows a void-free trenches filling.
