Novel advanced metal-oxide semiconductor (MOS) devices such as fully-depleted-silicon-on-insulator (FD-SOI) Tri-gate transistor, junctionless transistor, and amorphous-oxide-semiconductor thin film transistor were developed for continuing down-scaling trend and extending the functionality of CMOS technology, for example, the transparency and the flexibility. In this dissertation, the electrical characteristics and modeling of these advanced MOS devices are presented and they are analyzed. The sidewall mobility trends with temperature in multi-channel tri-gate MOSFET showed that the sidewall conduction is dominantly governed by surface roughness scattering. The degree of surface roughness scattering was evaluated with modified mobility degradation factor. With these extracted parameters, it was noted that the effect of surface roughness scattering can be higher in inversion-mode nanowire-like transistor than that of FinFET. The series resistance of multi-channel tri-gate MOSFET was also compared to planar device having same channel length and channel width of multi-channel device. The higher series resistance was observed in multi-channel tri-gate MOSFET. It was identified, through low temperature measurement and 2-D numerical simulation, that it could be attributed to the variation of doping concentration in the source/drain extension region in the device. The impact of channel width on back biasing effect in n-type tri-gate MOSFET on SOI material was also investigated. The suppressed back bias effects was shown in narrow device (Wtop_eff = 20 nm) due to higher control of front gate on overall channel, compared to the planar device (Wtop_eff = 170 nm). The variation of effective mobility in both devices was analyzed with different channel interface of the front channel and the back channel. In addition, 2-D numerical simulation of the the gate-to-channel capacitance and the effective mobility successfully reconstructed the experimental observation. The model for the effective mobility was inherited from two kinds of mobility degradations, i.e. different mobility attenuation along lateral and vertical directions of channel and additional mobility degradation in narrow device due to the effect of sidewall mobility. With comparison to inversion-mode (IM) transistors, the back bias effect on tri-gate junctionless transistors (JLTs) also has been investigated using experimental results and 2-D numerical simulations. Owing to the different conduction mechanisms, the planar JLT shows more sensitive variation on the performance by back biasing than that of planar IM transistors. However, the back biasing effect is significantly suppressed in nanowire-like JLTs, like in extremely narrow IM transistors, due to the small portion of bulk neutral channel and strong sidewall gate controls. Finally, the characterization method was comprehensively applied to a-InHfZnO (IHZO) thin film transistor (TFT). The series resistance and the variation of channel length were extracted from the transfer curve. And mobility values extracted with different methods such as split C-V method and modified Y-function were compared. The static characteristic evaluated as a function of temperature shows the degenerate behavior of a-IHZO TFT inversion layer. Using subthreshold slope and noise characteristics, the trap information in a-IHZO TFT was also obtained. Based on experimental results, a numerical model for a-IHZO TFT was proposed, including band-tail states conduction and interface traps. The simulated electrical characteristics were well-consistent to the experimental observations. For the practical applications of novel devices, the electrical characterization and proper modeling are essential. These attempts shown in the dissertation will provides physical understanding for conduction of these novel devices.
