With the constant decrease of dimensions in microelectronic devices, new problemes are raised. One of them is the variation of the transistor gate length, also called "Line Width Roughness" (LWR), which constitutes one of the most important sources of device variability. Regarding the future technological nodes, the LWR becomes a serious issue and should be reduced down to 2 nm. In this context, the acurate characterization of the LWR at the nanometric scale is essential but faces metrology tool limitations. At this scale, the equipment noise level can not be ignored.In order to compensate for this problem, a protocol allowing to get rid of the metrology equipment noise has been developped. It relies on the use of the discrete power spectral density, based on a "self affine fracal" autocorrelation function type. A "white" noise has been incorporated to the theoretical model, allowing the fitting of experimental data.The second issue concerns the significant LWR of the photoresist patterns printed by 193nm lithography, known to be partially transferred into the gate stack during the subsequent plasma etching steps. In order to solve this difficulty, plasma treatments have been applied to photoresists. Physico-chemical analysis of resists exposed to different plasma allowed us to observe that the UV emitted by the plama significantly smooth the resist sidewalls. On the other hand, the formation of a "stiff" layer around the patterns with some of the used plasma (namely HBr and Ar) leads to a degradation of the sidewall. New strategies have also been examined. Plasma treatments were especially combined to annealing treatments in order to couple their advantages. Finally, the H2 plasma appears as the most promissing for that it does not generate any surface "stiff" layer on the resist patterns and the UV significantly smooth the roughness. Combining this treatment with an annealing, it is possible to reach roughnesses as low as 2.4 nm in the final gate.
