A gate level methodology for efficient statistical leakage estimation in complex 32nm circuits
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | Design, Automation and Test in Europe (DATE) |
| Author | Joshi, Smriti, Lombardot, Anne, Belleville, Marc, Beigné, Edith, Girard, Stéphane |
| Maintainer | CCSD |
| Last Updated | May 12, 2026, 00:29 (UTC) |
| Created | May 12, 2026, 00:29 (UTC) |
| Identifier | hal-00805478 |
| Language | en |
| Rights | https://about.hal.science/hal-authorisation-v1/ |
| contributor | STMicroelectronics [Crolles] (ST-CROLLES) |
| coverage | Grenoble, France |
| creator | Joshi, Smriti |
| date | 2013-03-18T00:00:00 |
| harvest_object_id | b6b223ff-0399-4980-be7c-ae7d0db84fcc |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2025-09-27T00:00:00 |
| relation | info:eu-repo/semantics/altIdentifier/doi/10.7873/DATE.2013.221 |
| set_spec | type:COMM |