Computation of Wafer-At-Risk from Theory to Real Life Demonstration
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | Manufacturing Challenges in European Semiconductor Fabs |
| Author | Sahnoun, M'Hammed, Vialletelle, Philippe, Bassetto, Samuel, Tollenaere, Michel, Bastoini, Soidri |
| Maintainer | CCSD |
| Last Updated | May 22, 2026, 12:07 (UTC) |
| Created | May 22, 2026, 12:07 (UTC) |
| Identifier | hal-00685918 |
| Language | en |
| contributor | Système d’Information, conception RobustE des Produits (G-SCOP_SIREP) ; Laboratoire des sciences pour la conception, l'optimisation et la production (G-SCOP) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Rousset, France |
| creator | Sahnoun, M'Hammed |
| date | 2010-11-18T00:00:00 |
| harvest_object_id | 59da7b04-4e42-4094-b845-c56fd4b15696 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2025-09-27T00:00:00 |
| set_spec | type:COMM |