A Formal Method for Hardware IP Design and Integration under I/O and Timing Constraints

IP integration -that is one of the most important SoC design steps- requires taking into account communication and timing constraints. In that context design and reuse can be improved using IP cores described at a high abstraction level. In this paper we present an IP design approach that relies on three main phases: (1) constraint modeling, (2) IP constraint analysis steps for feasibility checking and (3) synthesis. We propose a set of techniques dedicated to the digital signal processing domain that lead to an optimized IP core integration. Based on a generic architecture of component, the method we propose provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach with a DCT core design case study.