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Development and characterization of plasma etch processes for TSV (Through Si...
The dictates of miniaturization and increased performance followed by microelectronics manufacturers faces currently physical, technological and economic limitations.... -
Characterization and modelling of 3D inteconnects HF performance for new gene...
The aim of this doctoral work is to study the new kind of interconnections like TSV (Through Silicon Via), redistribution lines (RDL) and copper pillars used in 3D... -
A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators
International audience -
Development of copper electroplating processes for Through Silicon Via (TSV) ...
Nowadays, 2D integration shows serious limitations when it comes to manufacturing devices with increased functionality and performance. In this context, 3D integration... -
Designing 3D tree-based FPGA: Interconnect Optimization and Thermal Analysis
International audience -
Selection of a precursor for the atomic layer deposition of copper : applicat...
With the increasing density of features in the various integrated circuits surrounding us, 3D integration (stacking chips) becomes essential. One key point of such... -
Built-In Self-Test for Manufacturing TSV Defects before bonding
International audience -
A BIST Method for TSVs Pre-Bond Test
International audience
