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Integration limits of etching masks and hybrid dielectric material for interc...
From 45 nm technological node, metallic interconnect lines of microelectronic circuits are isolated by low-k materials (porous SiOCH). These porous materials are... -
Three dimensional Stacking of Integrated circuits
During 50 years, semiconductor technology has been evolving in exponential rates in both productivity and performance. By following a steady technological path that... -
Post Etch Plasma Treatments used for Porous SiOCH Materials Integration for I...
The decrease of the integrated circuits size lets to increase the performances and reduce the manufacture costs. However, this shrink causes the preponderance of... -
Development of copper electroplating processes for Through Silicon Via (TSV) ...
Nowadays, 2D integration shows serious limitations when it comes to manufacturing devices with increased functionality and performance. In this context, 3D integration... -
Modeling and simulation of interconnects within and between electronic systems
The ongoing progress in transistor miniaturization and a continuous frequency increase are the main trends in the present day evolution of electronic circuits. A...
