Scaling technology in deep-submicron has reduced the voltage supply level and increased the number of transistors in the chip, increasing the power supply noise sensitivity of the ICs. Excessive power supply noise affects the timing performance increasing the gate delay and may cause timing faults. Specifically, power supply noise induced by the currents that flow through the resistive parasitic elements of the Power Distribution Network (PDN) is called IR-Drop. This thesis deals with the modelling and simulation of logic circuits in the context of IR-drop. An original algorithm is proposed allowing to perform an event-driven delay simulation of the logic Block Under Test (BUT) while taking into account the whole chip IR-drop impact on the simulated block. To do so, we develop accurate and efficient electrical models for the currents generated by the switching gates, the propagation of the current draw through the PDN and the gate delays. First, the pre-characterization process for the dynamic currents, static currents and gate delays is described to generate a gate library. Then, another pre-characterization procedure is suggested to estimate the current distribution through the resistive PDN model. Our models are implemented in a first version of the simulator by the University of Passau in the context of a project collaboration. In addition, the impact of the parasitic capacitive elements of the PDN is analyzed and a procedure to derive the current distribution in a resistive-capacitive PDN model is proposed.
