Chemical Mechanical Polishing (CMP), because of narrower specifications, as surface planarization at ± 5 nm, is becoming a critical process for the development of the 14 nm technology node and beyond. Habitual topographic characterization techniques, limited in acquisition area, appraise processes efficiency through structures called test boxes. Those structures have a size equal to 100 µm by 50 µm and they are located, in the scribe lines, between the chips. Consequently, they are not representative of the die level topography and die level topographic metrology processes are required. In a first time, we show that interferometric microscopy is able to characterize nano-topography over centimetric distances with micrometric lateral resolution. Interferometric microscopy characterization of CMP processes induced nano-topography demonstrates that usual methods provide non representative die level topography values. A new characterization kind related methodology is proposed and discussed. In a second time, we show that diffused light measurement allows fast (three minutes/wafer) and non-destructive control of gate nano-topography variations for pattern widths of some tenths of nanometer.
