Innovative underfills polymers for chips stacking

Since the invention of the transistor in the Fifties, performances of microelectronics components did not cease progressing thanks to their density increase. Unfortunately, miniaturization of components increases manufacturing costs in a prohibitory way. A solution, allowing densification and functionalization increase without costs rise, is microelectronics components stack. Their electrical connections are carried out using vertical interconnections welded by means of solder joints. In order to prevent their ruptures during thermal dilatations, interconnections are protected thanks to polymer underfill. The objective of this thesis is to evaluate the feasibility and the relevance of a new solution of polymer filling, called wafer-level underfill (WLUF). Flow of underfill during components assembly step is modeled in order to predict ideal bonding parameters, allowing electrical interconnections formation. Then, integration of new underfills, having different thermomechanical properties, being able to affect device integrity and functioning, the study of WLUF process reliability and, consequently, the evaluation of its industrialization possibility is carried out.

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Source https://theses.hal.science/tel-00965616
Author Taluy, Alisée
Maintainer CCSD
Last Updated May 5, 2026, 20:56 (UTC)
Created May 5, 2026, 20:56 (UTC)
Identifier NNT: 2013GRENI047
Language fr
Rights https://about.hal.science/hal-authorisation-v1/
contributor Laboratoire de Génie Electrique de Grenoble (G2ELab) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)
creator Taluy, Alisée
date 2013-12-18T00:00:00
harvest_object_id 0c159bca-cc6e-40b3-a6c9-7e1ae0b9ed64
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2026-03-31T00:00:00
set_spec type:THESE