Behavioral Analysis of switched capacitor filters for radiocommunications : Design of a new architecture in BiCMOS 0.35 μm technology

The main objective of the present research work is both to study the feasibility of radio-frequency monolithic switched capacitor filters for radio-communications, and to proceed to the analysis and design of these filters in the standard BiCMOS 0.35 μm technology. The behavioral analysis of these filters required the establishment of an original algorithm based on the conversion matrixes formalism, which in general principle consists of linearizing the non-linear elements around the operating points. This analysis method, especially used for the phase noise study of oscillator, seems to be among the most rigorous and efficient in term of calculation time for the analysis of this kind of filters in the present day. Traditionally, at low-frequencies the command of these filters is performed by using a shift register. However, this technique is not feasible in RF domain. An original solution has been proposed which consists in the use of a ring voltage controlled oscillator with " XOR " gates to command the filter. In the present thesis, it has been shown that the association of such command circuit with these filters presents some advantages which make it more attractive for designers. For the application in radiocommunication specifications, the classical structure of the switched capacitor filter has been optimized to reduce the noise figure and to increase the dynamic range, thus a new architecture (LC switched capacitor filter) has been proposed. The whole circuit has been simulated in the case of digital transmission (ex. p/4-DQPSK), the results have shown the adaptability for such kind of transmission. Moreover, the command circuit phase noise has been taken in account to study the jitter impact on the filter behavior. To validate the simulation results, a prototype consisted of an LC switched capacitor filter and its command circuit has been fabricated in standard BiCMOS 0.35 μm technology, the chip area is 1.1 x 1.75 mm². This first prototype has allowed to prove the feasibility of this architecture in the RF domain. The experimental results are in good agreement with simulations and are susceptible to render this original architecture attractive for RF applications.

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Source https://theses.hal.science/tel-00948226
Author El Oualkadi, Ahmed
Maintainer CCSD
Last Updated May 6, 2026, 08:33 (UTC)
Created May 6, 2026, 08:33 (UTC)
Identifier tel-00948226
Language fr
Rights https://about.hal.science/hal-authorisation-v1/
contributor Laboratoire d'automatique et d'informatique industrielle [EA 1219] (LAII [Poitiers]) ; Université de Poitiers = University of Poitiers (UP)
creator El Oualkadi, Ahmed
date 2004-12-08T00:00:00
harvest_object_id 7e94b3a8-e3b7-4b91-aaec-6f8ae5e43dc1
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2024-03-20T00:00:00
set_spec type:THESE