Design, optimization and integration of Doherty power amplifier for 3G/4G mobile communications

The signals of the new communication standards (LTE) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm.The circuit was designed with special attention to low cost.

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Source https://theses.hal.science/tel-00942844
Author Lajovic Carneiro, Marcos
Maintainer CCSD
Last Updated May 7, 2026, 02:25 (UTC)
Created May 7, 2026, 02:25 (UTC)
Identifier NNT: 2013BOR15024
Language en
Rights https://about.hal.science/hal-authorisation-v1/
contributor Laboratoire de l'intégration, du matériau au système (IMS) ; Université de Bordeaux (UB)-Institut Polytechnique de Bordeaux-Centre National de la Recherche Scientifique (CNRS)
creator Lajovic Carneiro, Marcos
date 2013-12-16T00:00:00
harvest_object_id e529cc0a-1f08-4e3b-9f35-fbf8151fd62e
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2026-03-31T00:00:00
set_spec type:THESE