The characteristics of Partially-Depleted SOI (PD-SOI) technology, as its speed improvement and the dielectric isolation of the transistors, turn to be interesting for input/output interface. However, using this technology leads to side effects, such as history effect, higher static consumption and self-heating effect. In this work, an analysis of these effects was carried out. Self-heating appears to be negligible. To address the two other effects, a solution with active body control has been proposed in order to suppress the history effect and to reduce the static consumption while keeping the speed improvement. The test chip, processed in PDSOI 65nm from STMicroelectronics, shows that the proposed solution improves the jitter during transmission. The second part of this work involves Fully-Depleted SOI (FD-SOI) technology. This technology brings a better electrostatic control of transistors and an additional degree of freedom for circuit design, thanks to threshold voltage control through back biasing. First, this feature has been validated on input/output circuit processed in FD-SOI 28nm from STMicroelectronics. Then, back biasing has been exploited for output impedance calibration and for environmental fluctuation compensation, based on LPDDR2 standard. The proposed solution in this work takes benefit of the impedance modulation through back biasing in order to perform the calibration during transmission, as opposed to the state-of-the-art techniques. Thus, the overall communication data rate increases.
