Hardware Control of partially reconfigurable FPGA-systems: from modeling to implementation

This work proposes a control design methodology for FPGA-based reconfigurable systems aiming at increasing control design productivity and guaranteeing implementation efficiency. This methodology is based on a semi-distributed control model composed of a set of modular distributed controllers executing each observation, decision-making and reconfiguration tasks for a reconfigurable region of the system, and a coordinator between the distributed controllers decisions in order to respect global systems constraints and objectives. This semi-distributed decision-making is based on the mode-automata formalism. The proposed combination between modularity, control splitting and formalism-based design allows to enhance the flexibility, reusability and scalability of the control design. Another point that can be added to this combination, to enhance design productivity, is design automation. For this, the proposed methodology is based on Model-Driven Engineering approach allowing to automate code generation from high-level models. This approach makes use of the UML MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard profile, allowing to make low-level technical details transparent to designers and to automate the VHDL code generation for hardware implementation of the modeled control systems in order to guarantee their performance. The generated control systems were validated using simulation. Synthesis results showed an acceptable time and resource overhead for systems having different numbers of controllers. A control system composed of four controllers and a coordinator was also validated through physical implementation in an FPGA system for an image processing application.

Data and Resources

Additional Info

Field Value
Source https://theses.hal.science/tel-00852361
Author Trabelsi, Chiraz
Maintainer CCSD
Last Updated May 10, 2026, 02:03 (UTC)
Created May 10, 2026, 02:03 (UTC)
Identifier tel-00852361
Language fr
Rights https://about.hal.science/hal-authorisation-v1/
contributor Dynamic Reconfigurable Massively Parallel Architectures and Languages (DREAMPAL) ; Université de Lille, Sciences et Technologies-Centre Inria de l'Université de Lille ; Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)
creator Trabelsi, Chiraz
date 2013-07-03T00:00:00
harvest_object_id 6ab4c463-f491-464d-960c-254c0ff4f2ad
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2025-02-26T00:00:00
set_spec type:THESE