Systems-on-chips in the field of digital communications are becoming extremely diversified and complex with the continuous emerging of new digital communication systems and standards. In this field, Turbo decoding is one of the most computation, communication, and memory intensive, and thus, power-consuming component. Besides the increasing performance requirements, emerging digital communication systems imply multi-standard interoperability which introduces the new implementation flexibility requirement. In this context, recent efforts have targeted the use of Application-Specific Instruction-set Processor models (ASIP). Such an architecture model enables the designer to freely tune the flexibility/performance trade-off as required by the considered application. However, the architecture efficiency of application-specific processors is directly related to the devised instruction set and pipeline stages usage. Most of recently proposed works do not present this key issue explicitly. Hence, the main objective of this thesis work is related to unifying flexibility-oriented and optimization-oriented approaches in the design of channel decoders. Towards this objective, several contributions have been proposed: (1) designing of a multi-standard ASIP-based Turbo decoder achieving high architecture efficiency in terms of bit/cycle/iteration/mm2, (2) optimizing of the dynamic reconfiguration speed of the proposed ASIP architecture supporting all parameters of 3GPP-LTE/WiMAX/DVB-RCS standards, (3) designing of low complexity ARP and QPP interleavers for butterfly scheme with Radix4 trellis compression technique, and (4) proposing and designing of a complete FPGA prototype for the proposed multi-standard Turbo decoder. Furthermore, towards the support of LDPC decoding, a first effort has been proposed for the design of a scalable and ¿exible high throughput multi-ASIP combined architecture for LDPC and Turbo decoding.
