Since the commercialization of the first integrated circuit in 1971, the microelectronic industry has fixed as an objective to reduce MOSFET transistor dimensions, following Moore's law. As indicated by Dennard, this miniaturization automatically improves device performances. Starting from the 28-22nm technological nodes, short channel effects are to strong and industrial companies choose to introduce new device structure: FDSOI for STMicroelectronics and Trigate for Intel. In such a context, CMOS technology performance evaluation is key and this thesis proposes to evaluate them at circuit level. Specific models for electrostatic parameters and parasitic capacitances for each device structure are developed for each device structure. Those models have first been used to evaluate performances of advanced technologies, such as III-V/Ge co-integration and 3D monolithic integration and have then been implemented in VerilogA to ensure compatibility with conventional CAD tools such as ELDO. This provides a compact model, predictive and usable for each device structure, which has been used to evaluated logic and SRAM performances of BULK, FDSOI and Trigate devices for the 20nm and 16nm technology node.
