The semiconductor industry has continued to make impressive improvements in the achievable density of very large-scale integrated (VLSI) circuits. In order to keep pace with the levels of integration available, design engineers have developed new methodologies and techniques to manage the increased complexity inherent in these large chips. One such emerging methodology is system-on-chip (SoC) design, wherein predesigned and preverified blocks (often called intellectual property (IP) blocks) are obtained from internal sources, or third parties and combined on a single chip. A library of reusable IP blocks with various timing, area, power configurations is the key to SoC success as the SoC integrator can apply the trade-offs that best suit the needs of the target application. Digital design has a well-defined, top-down design methodology but analog/mixed-signal (AMS) design has traditionally been an ad hoc custom design process. When analog and digital blocks coexist on the same substrate, the analog portion can be more time-consuming to develop even though it may represent a smaller percentage of the chip area. In this thesis, we present a hierarchical sizing and biasing methodology for analog intellectual properties. The proposed methodology addresses the problem of automatically generating suitable designs plans that are used to compute the DC operating point and dimensions for analog IPs. The methodology deals with different aspects of analog design problems such as insufficient degrees of freedom, systematic offset and negative feedback circuits. It has been used to successfully size and bias a variety of analog IPs and proved its precision and efficiency.
