Large variety of channel coding techniques are specified in existing and emerging digital communication standards, each suitable for specific application needs (frame size, transmission channel, signal-to-noise ratio, bandwidth, etc). Considering the emerging multi-mode and multi-standard applications, as well as the increasing interest for Software Defined Radio (SDR) and Cognitive Radio (CR) applications, flexible implementations combining multiple error correction techniques becomes mandatory. However, the need of optimal solutions in terms of performance, area, and power consumption is increasing too and cannot be neglected against flexibility. In this context, this thesis work has investigated multi-ASIP architecture model towards the target of unifying flexibility-oriented and optimization-oriented approaches in the design of flexible channel decoders. By considering mainly the challenging Turbo and LDPC decoding applications, multi-ASIP channel decoder architectures are proposed targeting high flexibility combined with high architecture efficiency in terms of bits/cycle/iteration/mm2. Different architecture alternatives and design approaches are explored. Three original contributions have been proposed. The first one concerns the design of a scalable and flexible high throughput multi-ASIP LDPC/Turbo decoder. Several design objectives have been attained in this work in terms of scalability, resource sharing, and configurability speed. The proposed DecASIP supports the decoding of LDPC and Turbo codes specified in WiFi, WiMAX, and LTE standards. The achieved scalability through the multi-ASIP NoC based approach enables the accommodation of current and future high throughput requirements. The second contribution concerns the design of a parameterized ASIP for Turbo decoding (TDecASIP). Here the objective was to investigate the maximum attainable architecture efficiency for ASIP-based Turbo decoding when maximizing the usage of sub-block parallelism. Furthermore, with this architecture we demonstrated the possibility to design application-specific parameterized cores using the available ASIP design flow. The third contribution corresponds to the design of an optimized ASIP for LDPC decoding (LDecASIP). As for TDecASIP, the objective was to investigate the maximum attainable architecture efficiency for ASIP-based LDPC decoding by increasing the parallelism degree and the necessary memory bandwidth. A fourth main contribution of this thesis work concerns the hardware prototyping. A complete communication system platform including 4-DecASIP channel decoder has been prototyped on an FPGA-based logic emulation board. To our knowledge, this is the first demonstrated multi-ASIP NoC-based FPGA prototype that is capable of decoding LDPC and Turbo (SBTC and DBTC) codes. Furthermore, an ASIC integration of the 4-DecASIP system decoder has been accomplished by the CEA-LETI on the MAG3D Telecom chip which targets 4G communication applications. These results demonstrate the rapid design cycle and the effectiveness offered by the ASIP based design approach in this application domain to fine tune design trade-offs w.r.t. diverse design objectives.
