Evolution of microelectronics follows several major roads, in particular the size decrease of active elements (reduction of size of transistors), better electrical performances, high I/O density and smaller size. This revolution has been predicted by Gordon Moore who suggested that integrated circuits would double in complexity every 24 months. As a consequence, this evolution induces both the reduction of prices and the weight of components.The term flip chip describes the method of electrically connecting the die to the package substrate. Flip chip microelectronic assembly is the direct electrical connection of face-down (or flipped) integrated circuit (IC) chips onto substrates, circuit boards, or carriers, using conductive bumps on the chip bond pads. Flip chip offers the highest speed electrical performance, reduces the delaying inductance and capacitance of the connection, Smallest Size Greatest I/O Flexibility, Most Rugged, high I/O density and Lowest Cost.This thesis work study concentrates on two main directions. The first one concerns hybridization by means of the technology of Indium bumps associated to a reflow process and the second one is about pressure induced hybridization at low temperature using nanostructures (Nano-scratch). In this work, we have developed a complete process to assemble a focal plane array format of 640 x 512 pixels with a pitch of 15 µm. These studies also allowed the mechanical validation of hybridization of a focal plane arrays 1280*1024 pixels with a pitch of 10 µm. Concerning alternative technologies to flip chip reflow, we introduced and demonstrate the relevance of a method of growth of ZnO nanorods using low temperature wet chemical growth and further hybridization at ambient temperature.
