High temperature CMOS SOI driver for JFET SiC transistors

In aeronautics, electrical systems progressively replace mechanical and hydraulic control systems. If the electronics can stand the absence of cooling, the immediate advantages will be the reduction of mass, increased performances, admissible reliability and thus reduction of costs. In aircraft, some important steps have already been performed successfully when substituting standard systems by electrical control system such as electrical brakes, thrust reverser, electrical actuators for flight control… Large band gap semiconductors (SiC, GaN…) have eased the operation in high temperature over the last decade and let overcome a weakness of conventional silicon systems (Si). High temperature power components such as Schottky diodes or JFET transistors, are already commercially available for a use up to 220°C, limited by package. Moreover inverters based on SiC JFET transistors have been realized and characterized at high temperature. Finally the control part of these power systems needs to be designed for harsh environment. It is in this context of lack of integrated control part that the FNRAE COTECH project and my doctoral research have been built. Based on a state of the art about drivers, the complex link between electronic and temperature and the potentialities of CMOS Silicon-On-Insulator technology (SOI) for high temperature applications have been underlined. The characterization of commercial SOI drivers gives essential data on these systems and their behavior at high temperature. These measurements also highlight the practical limitations of SOI technologies. The main part of this manuscript concerns the design and characterization of functions or IPs for high temperature JFET SiC driver. Two SOI runs in TFSmart1 have been realized. The developed functions include the driver output stage, associated buffers and protection functions. The drivers have been tested from -50°C up to 250°C without failure under short time-range. Moreover, an original protection function has been demonstrated against the short-circuit of an inverter leg. This function allows overcoming the main limitation of the normally on JFET transistor. Finally, an inverter module has been built for in-situ test of these new drivers.

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Source https://theses.hal.science/tel-00770657
Author Falahi, Khalil El
Maintainer CCSD
Last Updated May 15, 2026, 13:17 (UTC)
Created May 15, 2026, 13:17 (UTC)
Identifier NNT: 2012ISAL0056
Language fr
Rights https://about.hal.science/hal-authorisation-v1/
contributor Ampère (AMPERE) ; École Centrale de Lyon (ECL) ; Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL) ; Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon) ; Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
creator Falahi, Khalil El
date 2012-07-25T00:00:00
harvest_object_id b534ab23-4d16-4d15-bb3b-915d48f39985
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2026-03-31T00:00:00
set_spec type:THESE