The design of System on Chip mostly relies SstemC/C++. This language allows architectural and behavioural descriptions at different abstraction levels. Others approaches consider automated assembly of components into actual or virtual platforms (IP-Xact format). Using Model Driven Engineering techniques is a new trend, which may benefit form UML profiles (especially MARTE). In this thesis, we study the modelling power of these approaches and the possible bridges between them. SystemC provides a great deal of examples while MARTE offers facilities in system modelling at different levels. So, we try to export SystemC design to MARTE models. Beyond the mere conversion between formats, we propose an abstraction mechanism from SystemC code to models in IP-Xact formats. The IP-Xact description is then transformed into MARTE models with existing tools. We review related works and propose our solution leading to a dedicated tool called SCiPX (standing for SystemC to IP-Xact). In the second part of this thesis we apply the UML profile MARTE, its time model, and the associated language for specification of temporal constraints (CCSL° to specify interactions among components. A special attention is paid to protocol refinement. This study reveals a lack of CCSL for capturing the concept of priority. An improvement in the CCSL constraint solver is proposed to overcome this limitation.
