As device dimensions continue to shrink, RC delay in interconnects becomes more significant. This delay can be reduced by the use oflow dielectric constant (k) materials and low resistivity metals (Cu). The low k compatibility with different integration steps needs to be investigated. This work focuses on etch mechanisms and impact of ash processes on SiOCH material (porous and non porous) for their integration in single damascene architecture. This architecture is characterized physically and electrically. SiOCH etching is driven by a fluorocarbon interaction layer formed on top of the dielectric under plasma exposure. The formation of this fluorocarbon layer is governed by the plasma operating conditions (power injected in the plasma source, pressure and gas flow in the etch chamber), nature of the chemistry used and the chemical composition of the material itself. For porous materials reactive species can diffuse through the pores inducing a film modification. These modifications are increased during the ash step. ln this last case, a new ash chemistry needs to be developed allowing a trade off between the sidewall film modification required to prevent metal barrier diffusion and the increase in the dielectric constant.
