For more than 50 years, microelectronic industry is driven by a race to the miniaturisation of its central element, the MOS transistor, to improve the integration density, the performances and the cost of the electronic integrated circuits. Since the adoption of 100nm node, the only reduction of the dimensions of the transistor is no more sufficient and new technological modules (use of strain, high-k/metal gatestack…) have been introduced. However, conventional MOSFET, even opimized, will soon be unable to reach the specifications, always higher, of new technologies. Then, new structures should be considered to help and, finally, to replace the BULK technology. In this context, the work concerns the study, the fabrication and the electrical characterization of the thin film devices : Localized-SOI (LSOI) and planar gate-all-around (GAA). The obtained resultats point out the interest of such devices which allow the reduction of the leakage current (and thus the consumption), an excellent control of electrostatics and are able to work with an undoped channel while offering very good static performances. Impact of (110) substrates on transport properties in LSOI transistors is also studied. This work focuses on the integration of a full low-power platform, what induces the possibility of an hybrid integration with BULK devices and to offer several threshold voltages, everything on the same chip.
