The design of self-timed integrated circuits, including QDI (Quasi-Delay Insensitive) circuits, lead to robust circuits against variabilities in manufacturing processes and in running conditions (voltage, temperature). These qualities are consequences of the synthesys flow that does not create timing assumptions excepted a weak one related to isochronic forks. In self-timed circuits, the running speed automatically adjusts to the available supply voltage with no behavioral changes. This work focuses on the self-timed circuit robustness in the context of environments where running conditions can make QDI self-timed circuits failing. For instance, this happens when transition speeds at gate entrances become very slow. This uncommonly encountered situation can be triggered in harsh environments (with electromagnetic disturbences, high-energy particulesdots) or because of age effects on manufactured chips. If the integrated circuit is designed for critical operations such as in aeronautical, spatial or medical applications, the self-timed circuit limits have to be carrefully evaluated and eventually shifted in order to improve the circuit robustness. This publication includes a complete study of the self-timed circuit behaviors and some design proposals in order to enhance the circuit robustness. Experimental results were obtained firstly, during analog simulations targetting advanced CMOS technologies from STMicroelectronics and secondly, using formal methods implemented in a tool from the University of British Columbia.
