This thesis addresses the technical and technological challenges in the design of “all digital” reconfigurable mobile architectures operating cellular standard bands (GSM, WCDMA, HSUPA and LTE). With the ever-changing communication needs, mobile devices must be able to address different standards from a common architecture depending on free frequency bands, data rate and spectral constraints. In order to reduce costs, consumption and to obtain a greater integration, new architectures were developed and called multi-standard allowing a single transmitter to transmit each standard instead of parallelizing several radio architectures each dedicated to a particular standard. For several years nanoscale technologies such as 90nm or 65nm CMOS have emerged, clearing the way to replace analog functional blocks by greater digital functional blocks. In this study, we identify possible changes between "analog world" and "digital world" to move the digital boundary from the baseband to power amplifier. Several architectures have been studied with progressive digitization degrees to meet "all digital" architecture, comprising part of the power amplifier. Extensive work on the study of different cellular standards conducted jointly with the implementation and simulation of these architectures, let us identified the different technological and functional locks in the development of "all digital" architectures. Oversampling spurious constraints have emerged as dimensioning. For each band of each standard, these constraints were evaluated to define an optimization method of over-sampling frequency. However an external filter is required. A second step led us to identify and design a reconfigurable bandpass filtering technique for cellular bands from 1710 to 1980MHz with at least 60MHz of bandwidth in order to address the LTE, and 23dB attenuation at 390MHz from the center of the filter to address the most constringent filtering cases (bands 1, 3 and 10 in W-CDMA). We then designed and implemented a reconfigurable filter based on active inductors to ensure reconfigurability and very low insertion loss. This thesis permit from an actual architecture system issue and through a process to identify limitations of “all digital” architectures, to propose an adapted filtering solution. This filter was designed in 65nm CMOS, implemented. Measured performance is consistent with requirements
