Distributed PLL network for automatic clock synthesis of synchronous MPSOCs

The classical clock distribution trees used in the synchronous microprocessor systems in nowadays have several drawbacks such as skew, jitter, frequency limitation, perturbation and disturbance behavioral impact independently of their origin, etc.. These factors, critical for the modern microprocessors, motivate the research of an alternative architecture of the clock generation and distribution system. An example of such alternative architectures is the network of coupled PLLs where the PLLs are geographically distributed on the chip and produce the local clock signals. These local clock signals are then synchronized, in real time, by an exchange of information between the PLLs and by local feedback corrections realized by its controllers. Distributed PLLs network allows overcoming the mentioned limitation encountered for the classical clock distribution system. However, the active nature of this network requires going beyond the scope of usual stand-alone PLL design methods. Indeed, the dynamical aspects of the feedback loops and the transformations of the signal inside this complex system make the design problem extremely difficult to solve. The main issue consists in ensuring certain properties of the global network as well as local properties of each subsystem PLL because those properties may change drastically from independent stand-alone PLL designed with standard tools and methods. Indeed, depending on the network topology, the local properties and global dynamical behavior are not necessarily ensured for the overall network. The main contribution of this PhD thesis is the development of a control law design method for each subsystem (such as PLL) ensuring the desired behavior of the global network. A method for transforming the global design problem to an equivalent local control law design problem is proposed. It is based on the assumption that all subsystems are identical. The relation between the local and global properties is established using advanced Control System Theory tools such as input-output and dissipativity principle. This principle decreases significantly the problem complexity by transforming the design problem into a form that is closed to the design of a stand-alone closed loop system. The proposed method is combined with robust H∞ control and LMI optimization that can be solved efficiently with appropriate algorithms that are well suited for the considered application i.e. the PLLs network synchronization. The proposed approach can be easily generalized to other types of networked system to be controlled.

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Source https://theses.hal.science/tel-00676933
Author Korniienko, Anton
Maintainer CCSD
Last Updated May 25, 2026, 14:11 (UTC)
Created May 25, 2026, 14:11 (UTC)
Identifier NNT: 2011ECDL0040
Language fr
Rights https://about.hal.science/hal-authorisation-v1/
contributor Ampère (AMPERE) ; École Centrale de Lyon (ECL) ; Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL) ; Université de Lyon-Institut National des Sciences Appliquées de Lyon (INSA Lyon) ; Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-Institut National de Recherche pour l’Agriculture, l’Alimentation et l’Environnement (INRAE)
creator Korniienko, Anton
date 2011-12-06T00:00:00
harvest_object_id 2bb3e8f2-7364-49fb-97a8-f619c73eb5a1
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2026-03-30T00:00:00
set_spec type:THESE