tLIFTING : A Multi-level Delay-annotated Fault Simulator for Digital Circuits
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | DCIS 2012 - 27th Conference on Design of Circuits and Integrated Systems |
| Author | Di Natale, Giorgio, Flottes, Marie-Lise, Lu, Feng, Rouzeyre, Bruno |
| Maintainer | CCSD |
| Last Updated | May 12, 2026, 22:00 (UTC) |
| Created | May 12, 2026, 22:00 (UTC) |
| Identifier | lirmm-00799892 |
| Language | en |
| Rights | https://about.hal.science/hal-authorisation-v1/ |
| contributor | Conception et Test de Systèmes MICroélectroniques (SysMIC) ; Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM) ; Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Avignon, France |
| creator | Di Natale, Giorgio |
| date | 2012-11-28T00:00:00 |
| harvest_object_id | df20575c-9d90-4844-b93c-8d1c49a17f4b |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2025-08-13T00:00:00 |
| set_spec | type:POSTER |