Optimization of Number of Processors in VLSI Arrays

Since the work of Kung, the systolic architectures have proven their efficiency to deal with many scientific algorithms (LU-decomposition, Gauss-Jordan elimination, ...). Since the early eighties, many works have been made in the area of automatic derivation of systolic architectures. In the general case, there are numerous solutions to the same problem. The final choice of the architecture is often done by comparison of performances. There are several criteria which can be considered: global time of computation, number of processors, latency of the circuit... In this article we are especially interested with the number of processors of the final architecture for which we present a heuristic method.