The purpose of this document is to provide an analysis of the SAE standard AADL (AS5506) and submit recommendations for equipping it with a synchronous model of computation and communication (MoCC). Our goal is to provide a framework that best fits the semantic and expressive capability of the AADL, and is designed in a way that requires as few conceptual, semantic, or syntactic extensions as possible, on either the standard or its existing annexes. Our approach consists of the definition of an algebraic framework in which time is formally defined from implicit or specified AADL concepts, such as events. Starting from these concepts, that constitute the synchronous core of the AADL, we define a formal design methodology to use the AADL in a way that supports formal analysis, verification and synthesis of timed properties. By putting forward synchrony and timing, we intend to define time starting from software and hardware events that incur synchronisation in an architecture specification. Synchronisation indeed is the fundamental artefact from which time can be sensed, in either software or hardware. Synchrony relates to that fundamental concept as a model of computation and communication, applicable to both software and hardware design. It puts emphasis on logical time, abstracted through synchronisation points, in order to break down computations into zero-time reactions and regard communications as instantaneous. While abstracting real time, synchronous logical time provides an algebraic framework in which both event-driven and time-triggered execution policies can be specified. Bridging the gap between system-level, logical, synchronous specifications and time-triggered, distributed, and dynamically scheduled real-time applications necessitates a refinement-based design methodology, which we additionally intend to outline, to support the applicability of the proposed concepts in system design. To support the formal presentation of our MoCC, we define a algebra of automata consisting of transition systems and logical timing constraints. We consider the behaviour annex (BA) as the mean to implement this model, together with the constraint annex (CA), as a mean to represent abstractions of behaviour annexes using clock constraints and regular expressions.
