Modeling of signal integrity in bus communications with timed data flow SystemC-AMS
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | FDL 2013 - Forum on Specification Design Languages |
| Author | Wang, Ruomin, Denoulet, Julien, Feruglio, Sylvain, Vallette, Farouk, Garda, Patrick |
| Maintainer | CCSD |
| Last Updated | May 5, 2026, 19:15 (UTC) |
| Created | May 5, 2026, 19:15 (UTC) |
| Identifier | hal-00968667 |
| Language | en |
| contributor | Systèmes Electroniques (SYEL) ; Laboratoire d'Informatique de Paris 6 (LIP6) ; Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Paris, France |
| creator | Wang, Ruomin |
| date | 2013-09-24T00:00:00 |
| harvest_object_id | 5c6b4e2c-3a9e-406e-8217-2eb9eeec7f5e |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2025-10-14T00:00:00 |
| set_spec | type:COMM |