An overview: Dynamically reconfigurable fault tolerant FPGA architecture
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | GDR SoC-SiP CNRS |
| Author | Basheer Ahmed, Chagun Basha, Pillement, Sébastien |
| Maintainer | CCSD |
| Last Updated | May 6, 2026, 02:03 (UTC) |
| Created | May 6, 2026, 02:03 (UTC) |
| Identifier | hal-00957947 |
| Language | en |
| contributor | Institut d'Électronique et des Technologies du numéRique (IETR) ; Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes) ; Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Lyon, France |
| creator | Basheer Ahmed, Chagun Basha |
| date | 2013-06-10T00:00:00 |
| harvest_object_id | 42d87d4c-425c-411e-acb1-dccff868dc9b |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2023-03-24T00:00:00 |
| set_spec | type:COMM |