Process for making a gate for a short channel CMOS transistor structure
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | https://hal.science/hal-00944882 |
| Author | Joubert, O., Cunge, G., Foucher, J., Fuard, D., Bonvalot, M., Vallier, L. |
| Maintainer | CCSD |
| Last Updated | May 6, 2026, 21:02 (UTC) |
| Created | May 6, 2026, 21:02 (UTC) |
| Identifier | Patent N°: WO0205336 |
| Language | en |
| contributor | Laboratoire des technologies de la microélectronique (LTM) ; Université Joseph Fourier - Grenoble 1 (UJF)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Centre National de la Recherche Scientifique (CNRS) |
| creator | Joubert, O. |
| date | 2004-11-01T00:00:00 |
| harvest_object_id | 949db7f4-d22f-46a2-b3f0-9e79347d4759 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2025-09-27T00:00:00 |
| set_spec | type:PATENT |