Designing a NISC-based flexible architecture for MIMO MMSE-IC turbo-equalization

This paper presents a design of a custom architecture for a Minimum Mean Square Error Interference Cancellation (MMSE-IC) Linear Equalizer (LE) used in iterative MIMO turbo receiver using NO Instruction Set Computer (NISC) design approach. The proposed processor has a datapath, memory, and a simple controller with no instruction set or instruction decoder. NISC compiler schedules statically all operations and generates control values that must be driven to datapath components at every clock cycle and loads them in the memory. At runtime the controller only loads the control words and applies them to the datapath. The datapath consists of a computational unit, a storage unit and multiplexing unit. The allocation of hardware resources considered the required flexibility concerning the number of used antennas and the time selectivity of the channel. The design supports the MIMO use in 2×2, 3×3, and 4×4 spatial multiplexing configuration for block, quasi-static, and fast fading channel models.