Architecture Level TSV Count Minimization Methodology for 3D Tree-based FPGA
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | Cool Chips XVI |
| Author | Pangracious, Vinod, Mehrez, Habib, Marrakchi, Zied |
| Maintainer | CCSD |
| Last Updated | May 9, 2026, 09:01 (UTC) |
| Created | May 9, 2026, 09:01 (UTC) |
| Identifier | hal-00873268 |
| Language | en |
| Rights | https://about.hal.science/hal-authorisation-v1/ |
| contributor | Circuits Intégrés Numériques et Analogiques (CIAN) ; Laboratoire d'Informatique de Paris 6 (LIP6) ; Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Yokohama, Japan |
| creator | Pangracious, Vinod |
| date | 2013-04-17T00:00:00 |
| harvest_object_id | 03a47df0-794a-4f7d-89f0-f8768e22cb7e |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2023-04-11T00:00:00 |
| relation | info:eu-repo/semantics/altIdentifier/doi/10.1109/CoolChips.2013.6547925 |
| set_spec | type:COMM |