Pre- and post-scheduling memory allocation strategies on MPSoCs

6 pages

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Source Proceedings of The 2013 Electronic System Level Synthesis Conference (ESLSyn13)
Author Desnos, Karol, Pelcat, Maxime, Nezan, Jean François, Aridhi, Slaheddine
Maintainer CCSD
Last Updated May 9, 2026, 12:30 (UTC)
Created May 9, 2026, 12:30 (UTC)
Identifier hal-00868945
Language en
Rights https://about.hal.science/hal-authorisation-v1/
contributor Institut d'Électronique et des Technologies du numéRique (IETR) ; Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes) ; Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)
coverage Austin, TX, United States
creator Desnos, Karol
date 2013-05-31T00:00:00
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harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2023-03-24T00:00:00
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