Effect of die metallization layer ageing in the case of power semiconductor devices

The paper describes ageing mechanisms of the metallization layer deposited on the chips of power semiconductor devices, and the effects of its ageing on the electrical characteristics of a COOLMOSTM Transistor. We have tried to link the changes in electrical performances to the metallization degradation, in order to better understand the origin of the physical mechanisms of ageing and the effects of the degradation of the metallization layer on electrical performances of tested devices.

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Source ISSN: 2103-3641
Author Pommier, Sylvie, Lefebvre, Stéphane, Pietranico, Sylvain, Berkani, Mounira, Khatir, Zoubir, Bontemps, Serge, Cadel, Emmanuel
Maintainer CCSD
Last Updated May 9, 2026, 18:18 (UTC)
Created May 9, 2026, 18:18 (UTC)
Identifier hal-00861667
Language en
contributor Laboratoire de Mécanique et Technologie (LMT) ; École normale supérieure - Cachan (ENS Cachan)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)
creator Pommier, Sylvie
date 2011-01-01T00:00:00
harvest_object_id d7bd2f55-c16f-402a-ae9a-8b754d2fa5ae
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2025-08-14T00:00:00
relation info:eu-repo/semantics/altIdentifier/doi/10.3166/Geo.19.11-38
set_spec type:ART