Designing Robust Single-Chip Massively-Parallel Tera-Device Processors
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | Proc of 4th Design for Reliability Workshop (DFR) |
| Author | Nicolaidis, M. |
| Maintainer | CCSD |
| Last Updated | May 11, 2026, 09:35 (UTC) |
| Created | May 11, 2026, 09:35 (UTC) |
| Identifier | hal-00815969 |
| Language | en |
| contributor | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Paris, France |
| creator | Nicolaidis, M. |
| date | 2012-01-23T00:00:00 |
| harvest_object_id | 20d7be08-aa82-43ba-b419-caf9b80d199b |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2026-03-26T00:00:00 |
| set_spec | type:COMM |