Equivalent Circuit Synthesis Method for Reduced Order Models of Large Scale Inductive PEEC Circuits
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | CEFC 2012 |
| Author | Nguyen, Trung Son, Guichon, Jean-Michel, Chadebec, Olivier, Meunier, Gérard |
| Maintainer | CCSD |
| Last Updated | June 3, 2026, 23:20 (UTC) |
| Created | June 3, 2026, 23:20 (UTC) |
| Identifier | hal-00757554 |
| Language | en |
| contributor | Laboratoire de Génie Electrique de Grenoble (G2ELab) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Oita, Japan |
| creator | Nguyen, Trung Son |
| date | 2012-11-11T00:00:00 |
| harvest_object_id | 3720ea88-66b3-40d1-bd75-c91040f64d72 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2025-09-27T00:00:00 |
| set_spec | type:COMM |