Save energy and low power consumption for green communication become one of the most challenging design constraints in the research community for 65nm and below. As results, many power management techniques are developed throughout the design flow in order to assure low power consumption and the chip reliability. One of the most significant power related subjects that arise recently is power leakage. Leakage power forms a significant component of the total power dissipation especially for 65nm and below and due to within die variations in process, temperature and supply voltage. In this chapter, starting with the high correlation between chip temperature and leakage power consumption, associated with the possibility to move a processing element from a hot spot to a cooler one ( using Dynamic Partial Reconfiguration for example), we study this moving possibility so as to decrease leakage power consumption. The aim of this chapter is to conclude on the feasibility of this idea.
