A Fault-Tolerant Deadlock-Free Adaptive Routing for On Chip Interconnects

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Source Proc. of Design Automation and Test in Europe Conference (DATE'11)
Author Chaix, F., Avresky, D., Zergainoh, Nacer-Eddine, Nicolaidis, M.
Maintainer CCSD
Last Updated May 28, 2026, 04:53 (UTC)
Created May 28, 2026, 04:53 (UTC)
Identifier hal-00671500
Language en
contributor Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)
coverage Grenoble, France
creator Chaix, F.
date 2011-03-14T00:00:00
harvest_object_id 6aaddd6e-dc29-41aa-a974-e0d9ec99b1ac
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2026-03-26T00:00:00
set_spec type:COMM