Improving DPA resistance of Quasi Delay Insensitive Circuits using randomly time-shifted Acknowledgement Signals
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | 15th IFIP Int. Conf. on Very Large Scale Integration Systems, VLSI-SoC'05, October 17-19 |
| Author | Bouesse, Ghislain, Fraidy, Renaudin, Marc, Sicard, G. |
| Maintainer | CCSD |
| Last Updated | May 5, 2026, 15:22 (UTC) |
| Created | May 5, 2026, 15:22 (UTC) |
| Identifier | hal-00097712 |
| Language | en |
| contributor | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Perth, Australia |
| creator | Bouesse, Ghislain, Fraidy |
| date | 2005-05-05T00:00:00 |
| harvest_object_id | d66f3e51-5439-497d-81f6-554695c9cbf8 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2026-03-26T00:00:00 |
| set_spec | type:COMM |