A clock-less low-voltage AES crypto-processor
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European |
| Author | Bouesse, Ghislain, Fraidy, Renaudin, Marc, Witon, A., Germain, F. |
| Maintainer | CCSD |
| Last Updated | May 5, 2026, 18:33 (UTC) |
| Created | May 5, 2026, 18:33 (UTC) |
| Identifier | hal-00096996 |
| Language | en |
| contributor | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Grenoble, France |
| creator | Bouesse, Ghislain, Fraidy |
| date | 2005-05-05T00:00:00 |
| harvest_object_id | 906ed9ad-804c-4d74-9d98-2ef88bf89a79 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2026-03-26T00:00:00 |
| relation | info:eu-repo/semantics/altIdentifier/doi/10.1109/ESSCIR.2005.1541645 |
| set_spec | type:COMM |