A sampled spur free fractional frequency synthesizer and its noise analysis

This paper presents a new fractional frequency synthesizer architecture and its noise analysis model. The proposed analysis model takes into account the sampled behavior of the PLL. In order to validate this study, measurement results illustrate the output frequency purity and the reliability of the model.

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Source	Proceedings of ESSCIRC 2006, 32nd European Solid-State Circuits Conference, 18-22 September 2006, Montreux, Switzerland (2006).
Author	Houdebine, Marc, Dedieu, Sébastien, Sename, Olivier, Alamir, Mazen
Maintainer	CCSD
Last Updated	May 9, 2026, 13:55 (UTC)
Created	May 9, 2026, 13:55 (UTC)
Identifier	hal-00086709
Language	en
Rights	https://about.hal.science/hal-authorisation-v1/
contributor	Laboratoire d'automatique de Grenoble (LAG) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)
creator	Houdebine, Marc
date	2006-05-09T00:00:00
harvest_object_id	1d740a3d-3c58-40a3-821c-47e9f4a382fe
harvest_source_id	3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title	test moissonnage SELUNE
metadata_modified	2025-09-27T00:00:00
set_spec	type:COMM