Delay Correction in RTL Models of DSP SoC obtained by IP-based design approach
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | ISSN: 0752-4072 |
| Author | Zergainoh, Nacer-Eddine, Tambour, L., Michel, H., Jerraya, A.A. |
| Maintainer | CCSD |
| Last Updated | May 14, 2026, 06:59 (UTC) |
| Created | May 14, 2026, 06:59 (UTC) |
| Identifier | hal-00079196 |
| Language | fr |
| contributor | Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA) ; Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS) |
| creator | Zergainoh, Nacer-Eddine |
| date | 2005-05-14T00:00:00 |
| harvest_object_id | e58039bd-a8da-4bac-a351-2efe0c45c009 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2026-03-26T00:00:00 |
| set_spec | type:ART |
