A Memory Aware behavioral Synthesis Tool for Real-Time VLSI Circuits
Data and Resources
Additional Info
| Field | Value |
|---|---|
| Source | ACM Great Lake Symposium on VLSI |
| Author | Corre, Gwenolé, Julien, Nathalie, Martin, Eric, Senn, Eric |
| Maintainer | CCSD |
| Last Updated | May 15, 2026, 08:46 (UTC) |
| Created | May 15, 2026, 08:46 (UTC) |
| Identifier | hal-00077370 |
| Language | en |
| Rights | https://about.hal.science/hal-authorisation-v1/ |
| contributor | Laboratoire d'Electronique des Systèmes TEmps Réel (LESTER) ; Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS) |
| coverage | Boston, France |
| creator | Corre, Gwenolé |
| date | 2004-05-15T00:00:00 |
| harvest_object_id | 7617b85a-e1ce-47ef-8ab4-437cc710d745 |
| harvest_source_id | 3374d638-d20b-4672-ba96-a23232d55657 |
| harvest_source_title | test moissonnage SELUNE |
| metadata_modified | 2026-02-04T00:00:00 |
| set_spec | type:COMM |