High Level Ageing Vectors Management for Data Intensive Applications

We introduce a new approach to take into account the memory architecture and the memory mapping in behavioral synthesis. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate memory conflicts over several iterations of the algorithm. The final Compatibility Graph indicates the set of valid mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our strategy exhibits a relatively low complexity memory architecture for ageing vectors that permits to tackle complex designs for data intensive applications.

Data and Resources

Additional Info

Field Value
Source International Conference on Signals and Electronic Systems
Author Corre, Gwenolé, Senn, Eric, Julien, Nathalie, Martin, Eric
Maintainer CCSD
Last Updated May 15, 2026, 09:43 (UTC)
Created May 15, 2026, 09:43 (UTC)
Identifier hal-00077305
Language en
Rights https://about.hal.science/hal-authorisation-v1/
contributor Laboratoire d'Electronique des Systèmes TEmps Réel (LESTER) ; Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)
creator Corre, Gwenolé
date 2005-05-15T00:00:00
harvest_object_id 983d8700-0537-43fd-b98d-c28a8b361746
harvest_source_id 3374d638-d20b-4672-ba96-a23232d55657
harvest_source_title test moissonnage SELUNE
metadata_modified 2026-02-04T00:00:00
set_spec type:COMM